The present invention relates to a data comparison circuit comparing two binary coded digital signals, and more particularly to a circuit detecting whether or not two binary coded digital signals are coincident with each other.
In a digital circuit, a data comparison circuit is often employed to detect the coincidence between first and second binary coded digital signals. Since both of the signals to be compared have binary coded data, the detection of the coincidence is achieved by comparing all corresponding bits.
For this purpose, the comparison circuit in the prior art includes a plurality of exclusive-OR (called hereinafter as an "EX-OR") circuits receiving the comparing bit data and one logic circuit such as an NOR circuit, for example. The NOR circuit has a plurality of input terminals supplied with the outputs of the respective EX-OR circuits. When the logic level of each bit data of the first binary coded digital signal is equal to the corresponding bit data of the second binary coded digital signal, each of the EX-OR circuits takes the output of a low level. The NOR circuit thereby produces an output signal of a high level. On the other hand, if at least one of the bit data of the first signal is different in level from the corresponding bit data of the second signal, at least one EX-OR circuit produces the output of the high level. As a result, the output signal of the NOR circuit takes the low level. As well-known in the art, one EX-OR circuit constituted by the so-called complementary MOS transistors includes five P-channel transistors and five N-channel transistors. Assuming that each of the first and second digital signals has ten bits, ten EX-OR circuits are necessary, resulting in that one hundred transistors are required. In addition, the NOR circuit has ten input terminals, and requires ten P-channel transistors and ten N-channel transistors. As a result, the data comparison circuit in the prior art requires one hundred and twenty transistors in total. This means that considerably power is consumed in the comparison circuit and that the area occupied by the comparison circuit is large on a semiconductor integrated circuit chip.
Moreover, a wiring pattern for interconnecting the respective transistors is very complicated. Stray capacitances is thus large. As a result, the operation speed of the circuit is low.